## Lucid vs. Verilog

maelh
Posts: 2
Joined: June 3rd, 2017, 5:27 am

### Lucid vs. Verilog

Hi,

I have been reading the reference guide for Lucid, and done some tutorials for Verilog and Lucid.

Yet I could not really completely figure out what always does in each of those languages. Always is said to be about combinational logic in lucid, and the synchronous logic is probably just handled by the dff module.

That would explain why you always use = to assign to signal/ports in always blocks in Lucid. And <=, as known from Verilog, would only be used in dffs internally.

Still, I do not entirely know how to understand = in an always block of Lucid. Since it is combinational logic, it would appear that all happens asynchronously, like in a digital circuit made out of gates, that does not have flipflops in it.

Yet some things clearly are not parallel/asynchronous, since for example addition is a sequential process, if several bits are involved.

Somehow the distinction between what happens in parallel and what happens in sequence and what that sequence is remains a bit unclear. Is there some kind of reference that lists each and every case?

P.S.: Many thanks for the Mojo and software, it's been the easiest FPGA board to use and it's becoming continously better!
Last edited by maelh on September 13th, 2017, 7:00 pm, edited 1 time in total.

embmicro
Posts: 834
Joined: March 24th, 2013, 12:45 pm

### Re: Lucid vs. Verilog

The = and <= operators are a bit confusing to say the least. = is "blocking" while <= is "non-blocking". This just means that whatever you assign a value to with = you can assume it has that value after that line while <= updates at the end of the block.

In Lucid you never read and write to anything except a temporary signal, like in the addition example you mention. In Verilog you often read and write the same signal but you don't want the write to happen until the end of the block (for flip-flops).

The important thing to remember is that you are simply describing a behavior when you are writing always blocks. There may or may not be a 1-1 physical signal to design signal mapping.

I hope this helps!
Justin

maelh
Posts: 2
Joined: June 3rd, 2017, 5:27 am

### Re: Lucid vs. Verilog

Thanks. One follow up question: what is a temporary and what is a non-temporary signal?

For future reference: the part regarding always blocks in the following link helps a bit: https://en.wikibooks.org/wiki/Programma ... ing_values

embmicro
Posts: 834
Joined: March 24th, 2013, 12:45 pm

### Re: Lucid vs. Verilog

By temporary I just mean a result used within and only within an always block. For example...

Code: Select all

``````sig x;

always {
x = a + b;
out = x;
}``````
x is what I called "temporary" because it's really just the name for the connection between the adder and the output. It doesn't store any value. In this case the assignment is "blocking" so that the addition happens "first". It doesn't actually happen first but when the tools look at the always block that's how it is interpreted to get the behavior you want. A non-blocking assignment requires some kind of memory in your circuit because the value you read from x isn't directly available (as it typically comes from the previous clock cycle).