AVR Interface CCLK line

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AVR Interface CCLK line

Post by mclem5 » September 24th, 2017, 6:07 pm

I just started messing with the Mojo V3 board. I have looked over the mojo base files, I also found the base file converted into VHDL and I used that to do the LED blink demo. I am thankful this files were given to the embedded micro community, however I am going through them and trying to understand all that is happening since I would like to eventually build those files on my own.

One question I have is how do you know that we must wait 512 cycles of the CCLK (SCL) line being high before the FGPA can take control of its outputs? I was looking through the atmel datasheet and I did not see where it mentioned this. I am also confused because SCL is a clock line, why would this line stay high? I see in the timing diagrams it looks like it shows it staying high until the SDA line is pulled low.

I appreciate the help.

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Re: AVR Interface CCLK line

Post by embmicro » October 30th, 2017, 12:56 pm

CCLK is used when the AVR configures the FPGA. The delay is there to make sure the FPGA doesn't start pulling on pins that are still an output for the AVR (as it finishes up the configuration). Basically this delay gives the AVR time to switch pins that are outputs during configuration to inputs for post-configuration use.

The CCLK pin isn't used as a clock. If I recall correctly, the SCL use applies when you use the serial port as a synchronous port but the Mojo uses it asynchronously so it's not used.

CCLK is configuration clock too if that wasn't clear. It is the clock used to send the configuration data into the FPGA. It is normally idle low but the AVR will pull it high when it is done configuring the FPGA. By waiting a decent amount of time we can sure the AVR is actually done and it won't toggle low again.

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