verilog problem

Projects you are planning or working on with the Mojo
Post Reply
Posts: 1
Joined: January 20th, 2016, 4:25 am

verilog problem

Post by priyesh » January 20th, 2016, 4:31 am

in verilog when we fetch data from rom to other at that time why we can not reset the signal in main code?

Site Admin
Posts: 834
Joined: March 24th, 2013, 12:45 pm

Re: verilog problem

Post by embmicro » January 20th, 2016, 1:13 pm

I'm not sure what you're asking. Maybe give us an example?

Post Reply