for loop symbol expansion?

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Tinkerer
Posts: 7
Joined: October 5th, 2014, 1:34 pm

for loop symbol expansion?

Post by Tinkerer » December 27th, 2016, 5:33 pm

I'm making some logic to drive a number of servos. I have some code that looks like:

.clk(clk), .rst(rst) {
servo s0;
servo s1;
// etc.
}

I was wondering if it was possible, in Lucid, to declare each of the servos with a for loop?

Thanks

otzen42
Posts: 46
Joined: March 1st, 2014, 2:37 pm

Re: for loop symbol expansion?

Post by otzen42 » January 1st, 2017, 10:49 am

What your looking for is the generate statement. I'm not familiar with Lucid, but here is a simple example in standard Verilog where a generate block is used to instantiate multiple copies of a module (lines 27-35 of the first code snipet):

http://www.asic-world.com/verilog/verilog2k2.html

Note that the ": MEM" after the begin is just an optional name for the generate loop. It is a good idea to put a name on each loop if you multiple though, it makes signals easier to find than if syntheses gives all the loops generic names.

embmicro
Site Admin
Posts: 834
Joined: March 24th, 2013, 12:45 pm

Re: for loop symbol expansion?

Post by embmicro » January 5th, 2017, 2:06 pm

In Lucid you simply make an array of the modules (it's implemented in a generate statement).

Code: Select all

.clk(clk), .rst(rst) {
servo s[8]; // eight servo modules
}
This packs the inputs and outputs to each module into an array or a multidimensional array if it was already an array. The first index will be the module index. For example, if "servo" has an input "value" that is eight bits wide you could do this.

Code: Select all

s.value[0] = 8h01;
 s.value = {8h01, 8h02, 8h03, 8h04, 8h01, 8h02, 8h03, 8h04};

Tinkerer
Posts: 7
Joined: October 5th, 2014, 1:34 pm

Re: for loop symbol expansion?

Post by Tinkerer » February 12th, 2017, 7:28 pm

I'm still unable to make this work.

Specifically, when I use outputs from array of modules. For example, for an array axis[] that I'm using to abstract the servo positions, when I write things like this (no for loop variable needed to stimulate the problem):

sig offset[6][PRECISION];

offset[0] = axis[0].offset;

the 'axis[0].offset' has its '0' underlined by the IDE. Hovering over that zero, I get a notice "This bit selector should not be here". This is not supposed to be a bit selector, this is supposed to be the zeroth axis in my array of modules.

Am I writing this incorrectly?

Tinkerer
Posts: 7
Joined: October 5th, 2014, 1:34 pm

Re: for loop symbol expansion?

Post by Tinkerer » February 12th, 2017, 7:45 pm

Here is a simple top level example (see // *** ):

Code: Select all

  ....
  sig rst;                  // reset signal
  
  .clk(clk) {
    // The reset conditioner is used to synchronize the reset signal to the FPGA
    // clock. This ensures the entire FPGA comes out of reset at the same time.
    reset_conditioner reset_cond;
    servo s[8];
  }
  
  var i;
  
  always {
    reset_cond.in = ~rst_n; // input raw inverted reset signal
    rst = reset_cond.out;   // conditioned reset
    
    for (i=0; i<8; i++) {
      s[i].position = 23; // *** "This bit selector should not be here"
      led[i] = s[i].servo;  // *** "This bit selector should not be here"
    }
    
    spi_miso = bz;          // not using SPI
    spi_channel = bzzzz;    // not using flags
    avr_rx = bz;            // not using serial port
  }

Tinkerer
Posts: 7
Joined: October 5th, 2014, 1:34 pm

Re: for loop symbol expansion?

Post by Tinkerer » February 12th, 2017, 7:59 pm

Humble pie. Reading over your response I now see I need to put the index elsewhere:

Code: Select all

  for (i=0; i<8; i++) {
      s.position[i] = 23;
      led[i] = s.servo[i];
    }
Perhaps a specific example of this could be inserted into the myCounter[8] example of defining array modules in the Lucid description?

Thanks

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