Why are the physical pin numbers of the FPGA referenced in the I/O shield schematic back to front when compared to the io_shield.ucf file ?
e.g. in the .ucf file, the NET reference to dip<0> is pin 120 but the schematic routes to [dip24].
Am I missing something very obvious or is the physical mapping changed from Big-endian to Little-endian in the .ucf file ?
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