Process "Synthesize - XST" failed

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antgi1
Posts: 1
Joined: December 9th, 2017, 6:56 pm

Process "Synthesize - XST" failed

Post by antgi1 » December 9th, 2017, 7:03 pm

Hi, im trying to synthesize the blinker example on the ISE but get only a Process "Synthesize - XST" failed message

I run on windows 10. I basically used the code given on the tutorials (copypaste).
Would anyone know what is my problem? The same happens with the base project. Furthermore, in the Mojo IDE building has no effect, no .bin files get generated and i get no results.

Thank you very much in advance. I followed the instructions line by line but i dont get a working result.

I get the following summary file:


Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "C:/Users/Antonio Banderas/Desktop/FPGA/mojonew/mojo-base-project-master/syn/mojo_top.xst" -ofn "C:/Users/Antonio Banderas/Desktop/FPGA/mojonew/mojo-base-project-master/syn/mojo_top.syr"
Reading design: mojo_top.prj

=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "C:\Users\Antonio Banderas\Desktop\FPGA\mojonew\mojo-base-project-master\blinker.v" into library work
Parsing module <blinker>.
Analyzing Verilog file "C:\Users\Antonio Banderas\Desktop\FPGA\mojonew\mojo-base-project-master\src\mojo_top.v" into library work
Parsing module <mojo_top>.

=========================================================================
* HDL Elaboration *
=========================================================================

Elaborating module <mojo_top>.

Elaborating module <blinker>.

=========================================================================
* HDL Synthesis *
=========================================================================

Synthesizing Unit <mojo_top>.
Related source file is "C:\Users\Antonio Banderas\Desktop\FPGA\mojonew\mojo-base-project-master\src\mojo_top.v".
WARNING:Xst:647 - Input <cclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_ss> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_mosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_sck> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <avr_tx> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <avr_rx_busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit tristate buffer for signal <spi_miso> created at line 26
Found 1-bit tristate buffer for signal <avr_rx> created at line 27
Found 1-bit tristate buffer for signal <spi_channel<3>> created at line 28
Found 1-bit tristate buffer for signal <spi_channel<2>> created at line 28
Found 1-bit tristate buffer for signal <spi_channel<1>> created at line 28
Found 1-bit tristate buffer for signal <spi_channel<0>> created at line 28
Summary:
inferred 6 Tristate(s).
Unit <mojo_top> synthesized.

Synthesizing Unit <blinker>.
Related source file is "C:\Users\Antonio Banderas\Desktop\FPGA\mojonew\mojo-base-project-master\blinker.v".
Found 25-bit register for signal <counter_q>.
Found 25-bit adder for signal <counter_d> created at line 12.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 25 D-type flip-flop(s).
Unit <blinker> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors : 1
25-bit adder : 1
# Registers : 1
25-bit register : 1
# Tristates : 6
1-bit tristate buffer : 6

=========================================================================

=========================================================================
* Advanced HDL Synthesis *
=========================================================================


Synthesizing (advanced) Unit <blinker>.
The following registers are absorbed into counter <counter_q>: 1 register on signal <counter_q>.
Unit <blinker> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters : 1
25-bit up counter : 1

=========================================================================

=========================================================================
* Low Level Synthesis *
=========================================================================

Optimizing unit <mojo_top> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mojo_top, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers : 25
Flip-Flops : 25

=========================================================================

=========================================================================
* Partition Report *
=========================================================================

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================
* Design Summary *
=========================================================================

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 25 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

Minimum period: 2.491ns (Maximum Frequency: 401.485MHz)
Minimum input arrival time before clock: 4.125ns
Maximum output required time after clock: 4.162ns
Maximum combinational path delay: No path found

=========================================================================

Process "Synthesize - XST" failed

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