Mojo IDE won't build basic examples

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th3j3ster
Posts: 5
Joined: April 24th, 2017, 7:51 pm

Mojo IDE won't build basic examples

Post by th3j3ster » April 24th, 2017, 7:58 pm

Hi guys,

I'm having a strange issue. I've installed the Mojo IDE version BV1.3.6, and I've tried to build both the "Base Project" and "LED to Button" projects, but the build sequence fails for both. I can't see anything wrong with the Lucid I have. I'm posting the error message I'm getting below; if requested I can post the full build output or .luc file I'm trying to run (although it's identical to the example as I haven't altered anything). I've also tried to uninstall and reinstall the IDE with no success, and I've successfully built the example project in the ISE and flashed that onto the mojo without issue.

Here's the error:

Code: Select all

=========================================================================
[Mon Apr 24 20:49:04 2017] synth_1 finished
wait_on_run: Time (s): elapsed = 00:00:10 . Memory (MB): peak = 143.059 ; gain = 0.000
# launch_runs -runs impl_1
ERROR: [Common 17-69] Command failed: Parent run 'synth_1' needs to be run before 'impl_1' can be launched

    while executing
"launch_runs -runs impl_1"

embmicro
Site Admin
Posts: 834
Joined: March 24th, 2013, 12:45 pm

Re: Mojo IDE won't build basic examples

Post by embmicro » April 27th, 2017, 2:54 pm

Please post the reset of the output. I am able to build these with B1.3.6 so it may be a problem with ISE.

th3j3ster
Posts: 5
Joined: April 24th, 2017, 7:51 pm

Re: Mojo IDE won't build basic examples

Post by th3j3ster » April 28th, 2017, 5:04 am

Sure thing!

Code: Select all

Warnings in file mojo_top.luc:
    Line 5, Column 4 : "cclk" was never used
    Line 13, Column 4 : "avr_rx_busy" was never used
    Line 8, Column 4 : "spi_mosi" was never used
    Line 9, Column 4 : "spi_sck" was never used
    Line 11, Column 4 : "avr_tx" was never used
    Line 7, Column 4 : "spi_ss" was never used

****** PlanAhead v14.7 (64-bit)
  **** Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
source {D:\My Files\Documents\mojo\TestingBuild\work\project.tcl}
# set projDir "D:/My Files/Documents/mojo/TestingBuild/work/planAhead"
# set projName "TestingBuild"
# set topName top
# set device xc6slx9-2tqg144
# if {[file exists "$projDir/$projName"]} { file delete -force "$projDir/$projName" }
# create_project $projName "$projDir/$projName" -part $device
# set_property design_mode RTL [get_filesets sources_1]
# set verilogSources [list "D:/My Files/Documents/mojo/TestingBuild/work/verilog/mojo_top_0.v" "D:/My Files/Documents/mojo/TestingBuild/work/verilog/reset_conditioner_1.v"]
# import_files -fileset [get_filesets sources_1] -force -norecurse $verilogSources
# set ucfSources [list  "C:/Program\ Files/Mojo\ IDE/library/components/mojo.ucf"]
# import_files -fileset [get_filesets constrs_1] -force -norecurse $ucfSources
# set_property -name {steps.bitgen.args.More Options} -value {-g Binary:Yes -g Compress} -objects [get_runs impl_1]
# set_property steps.map.args.mt on [get_runs impl_1]
# set_property steps.map.args.pr b [get_runs impl_1]
# set_property steps.par.args.mt on [get_runs impl_1]
# update_compile_order -fileset sources_1
# launch_runs -runs synth_1
[Fri Apr 28 05:59:26 2017] Launched synth_1...
Run output will be captured here: D:/My Files/Documents/mojo/TestingBuild/work/planAhead/TestingBuild/TestingBuild.runs/synth_1/runme.log
# wait_on_run synth_1
[Fri Apr 28 05:59:26 2017] Waiting for synth_1 to finish...

*** Running xst
    with args -ifn "mojo_top_0.xst" -ofn "mojo_top_0.srp" -intstyle ise

Reading design: mojo_top_0.prj

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "D:/My Files/Documents/mojo/TestingBuild/work/planAhead/TestingBuild/TestingBuild.srcs/sources_1/imports/verilog/reset_conditioner_1.v" into library work
Parsing module <reset_conditioner_1>.
Analyzing Verilog file "D:/My Files/Documents/mojo/TestingBuild/work/planAhead/TestingBuild/TestingBuild.srcs/sources_1/imports/verilog/mojo_top_0.v" into library work
Parsing module <mojo_top_0>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <mojo_top_0>.

Elaborating module <reset_conditioner_1>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mojo_top_0>.
    Related source file is "D:/My Files/Documents/mojo/TestingBuild/work/planAhead/TestingBuild/TestingBuild.srcs/sources_1/imports/verilog/mojo_top_0.v".
WARNING:Xst:647 - Input <cclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_ss> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_mosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_sck> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <avr_tx> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <avr_rx_busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit tristate buffer for signal <spi_miso> created at line 34
    Found 1-bit tristate buffer for signal <spi_channel<3>> created at line 34
    Found 1-bit tristate buffer for signal <spi_channel<2>> created at line 34
    Found 1-bit tristate buffer for signal <spi_channel<1>> created at line 34
    Found 1-bit tristate buffer for signal <spi_channel<0>> created at line 34
    Found 1-bit tristate buffer for signal <avr_rx> created at line 34
    Summary:
	inferred   6 Tristate(s).
Unit <mojo_top_0> synthesized.

Synthesizing Unit <reset_conditioner_1>.
    Related source file is "D:/My Files/Documents/mojo/TestingBuild/work/planAhead/TestingBuild/TestingBuild.srcs/sources_1/imports/verilog/reset_conditioner_1.v".
    Found 4-bit register for signal <M_stage_q>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <reset_conditioner_1> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 4-bit register                                        : 1
# Tristates                                            : 6
 1-bit tristate buffer                                 : 6

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 4
 Flip-Flops                                            : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <mojo_top_0> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block mojo_top_0, actual ratio is 0.

Final Macro Processing ...

Processing Unit <mojo_top_0> :
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <reset_cond/M_stage_q_3> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <mojo_top_0> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 4
 Flip-Flops                                            : 4

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 1.280ns (Maximum Frequency: 781.250MHz)
   Minimum input arrival time before clock: 3.526ns
   Maximum output required time after clock: 4.118ns
   Maximum combinational path delay: No path found

=========================================================================
[Fri Apr 28 05:59:36 2017] synth_1 finished
wait_on_run: Time (s): elapsed = 00:00:10 . Memory (MB): peak = 143.160 ; gain = 0.000
# launch_runs -runs impl_1
ERROR: [Common 17-69] Command failed: Parent run 'synth_1' needs to be run before 'impl_1' can be launched

    while executing
"launch_runs -runs impl_1"
    (file "D:\My Files\Documents\mojo\TestingBuild\work\project.tcl" line 19)
INFO: [Common 17-206] Exiting PlanAhead at Fri Apr 28 05:59:36 2017...
INFO: [Common 17-83] Releasing license: PlanAhead

Finished building project.

oter
Posts: 4
Joined: May 2nd, 2017, 12:40 am

Re: Mojo IDE won't build basic examples

Post by oter » May 2nd, 2017, 12:47 am

Running into the same problem. Running mojo-ide B1.3.6, ISE 14.7, Ubuntu 16.04 (via VMWare Fusion on OSX).

*** Running xst
with args -ifn mojo_top_0.xst -ofn mojo_top_0.srp -intstyle ise

Reading design: mojo_top_0.prj

=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "/home/reto/mojo/LEDToButton/work/planAhead/LEDToButton/LEDToButton.srcs/sources_1/imports/verilog/reset_conditioner_1.v" into library work
Parsing module <reset_conditioner_1>.
Analyzing Verilog file "/home/reto/mojo/LEDToButton/work/planAhead/LEDToButton/LEDToButton.srcs/sources_1/imports/verilog/mojo_top_0.v" into library work
Parsing module <mojo_top_0>.

=========================================================================
* HDL Elaboration *
=========================================================================

Elaborating module <mojo_top_0>.

Elaborating module <reset_conditioner_1>.

=========================================================================
* HDL Synthesis *
=========================================================================

Synthesizing Unit <mojo_top_0>.
Related source file is "/home/reto/mojo/LEDToButton/work/planAhead/LEDToButton/LEDToButton.srcs/sources_1/imports/verilog/mojo_top_0.v".
WARNING:Xst:647 - Input <cclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_ss> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_mosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spi_sck> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <avr_tx> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <avr_rx_busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit tristate buffer for signal <spi_miso> created at line 34
Found 1-bit tristate buffer for signal <spi_channel<3>> created at line 34
Found 1-bit tristate buffer for signal <spi_channel<2>> created at line 34
Found 1-bit tristate buffer for signal <spi_channel<1>> created at line 34
Found 1-bit tristate buffer for signal <spi_channel<0>> created at line 34
Found 1-bit tristate buffer for signal <avr_rx> created at line 34
Summary:
inferred 6 Tristate(s).
Unit <mojo_top_0> synthesized.

Synthesizing Unit <reset_conditioner_1>.
Related source file is "/home/reto/mojo/LEDToButton/work/planAhead/LEDToButton/LEDToButton.srcs/sources_1/imports/verilog/reset_conditioner_1.v".
Found 4-bit register for signal <M_stage_q>.
Summary:
inferred 4 D-type flip-flop(s).
Unit <reset_conditioner_1> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers : 1
4-bit register : 1
# Tristates : 6
1-bit tristate buffer : 6

=========================================================================

=========================================================================
* Advanced HDL Synthesis *
=========================================================================

FATAL_ERROR:Xst:Port_Main.h:159:1.18 - This application has discovered an exceptional condition from which it cannot recover. For technical support on this issue, please visit http://www.xilinx.com/support.

oter
Posts: 4
Joined: May 2nd, 2017, 12:40 am

Re: Mojo IDE won't build basic examples

Post by oter » May 3rd, 2017, 8:11 pm

Seeing the same "ERROR: [Common 17-69] Command failed: Parent run 'synth_1' needs to be run before 'impl_1' can be launched".
Any ideas of what might cause it (workarounds)?

oter
Posts: 4
Joined: May 2nd, 2017, 12:40 am

Re: Mojo IDE won't build basic examples

Post by oter » May 5th, 2017, 2:31 pm

Switching to the older Ubuntu 14.04 resolved the problem, I previously reported. LEDToButton sample now works.

th3j3ster
Posts: 5
Joined: April 24th, 2017, 7:51 pm

Re: Mojo IDE won't build basic examples

Post by th3j3ster » May 6th, 2017, 9:29 pm

embmicro wrote:Please post the reset of the output. I am able to build these with B1.3.6 so it may be a problem with ISE.
Any idea what could be causing this? it definitely seems like synth_1 is finishing before impl_1 attempts to run, so I'm not sure what else to try/check.

embmicro
Site Admin
Posts: 834
Joined: March 24th, 2013, 12:45 pm

Re: Mojo IDE won't build basic examples

Post by embmicro » May 8th, 2017, 2:02 pm

Is anyone having this issue not using Ubuntu 16.04?

th3j3ster
Posts: 5
Joined: April 24th, 2017, 7:51 pm

Re: Mojo IDE won't build basic examples

Post by th3j3ster » May 13th, 2017, 8:11 pm

embmicro wrote:Is anyone having this issue not using Ubuntu 16.04?
I'm not. I'm running the Mojo IDE/ISE on windows 10.

embmicro
Site Admin
Posts: 834
Joined: March 24th, 2013, 12:45 pm

Re: Mojo IDE won't build basic examples

Post by embmicro » May 16th, 2017, 11:49 am

There's known issues with the latest Windows 10 preview patch that breaks ISE. I haven't found a workaround for it yet.

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