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trouble when using Verilog in first tutorial

Posted: July 27th, 2018, 2:56 pm
by Tommasino
Hello,
To link pushbutton to single LED, I tried code that worked under Lucid, though adding "assign" to fit what I'm accustomed to in Verilog:
// can I just drive one bit of the 8, using index?
assign led[0] = rst;
// and send the other 7 LEDs low (off, I guess)
assign led[7:1] = 0;

Why does this "assign" fail?

Trying to build this, I get this error:
ERROR: [Common 17-69] Command failed: Parent run 'synth_1' needs to be run before 'impl_1' can be launched

Thanks
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Here's some more of the code, including the "assign" that does work, one provided by Embedded in this verilog project 1:
...
assign led = 8'b0; // this works
// led = 8h00; // turn LEDs off
// per tutorial, set up LSB as single LED output, using concatenate
// but now that we're in Verilog, try using "assign"; then try without 'assign'
// led = c{7h00, rst};// this fails under Verilog, "mismatched input"
// Palnitkar concatenate example omits the "c"
// led = {7h00, rst}; // this fails, too, under Verilog
// can I just drive one bit of the 8, using index?
assign led[0] = rst;
// and send the other 7 LEDs low (off, I guess)
assign led[7:1] = 0;


ERROR: [Common 17-69] Command failed: Parent run 'synth_1' needs to be run before 'impl_1' can be launched