Page 1 of 1

Clocks and CoreGen 50Mhz > 150Mhz

Posted: December 8th, 2016, 8:32 am
by jkane6666

I am new to this so be gentle, I am trying to use coregen to change the clock frequency from 50 Mhz to 150 Mhz, I am generating a few frequencys, ie square waves, the best I can get at 50Mhz is 40ns, but I need about 10ns, so it seems that coregen is the way to go. but it does not work for me.

Here is my code

module tone_tester(
input clk,
output tone_1khz,
output tone_100hz,
output tone_12khz

reg [31:0] period_1khz = 1000;
reg [31:0] period_100hz = 10000;
reg [31:0] period_12khz = 1; //80;

tone #(50) t1(.clk (clk), .period (period_1khz), .tone_out (tone_1khz));
tone #(50) t2(.clk (clk), .period (period_100hz), .tone_out (tone_100hz));
tone #(50) t3(.clk (clk), .period (period_12khz), .tone_out (tone_12khz));


module tone(
input clk,
input[31:0] period,
output reg tone_out

reg [31:0] counter = 0;

always @(posedge clk)
if (counter == period)
counter <= 0;
tone_out <= ~ tone_out;
counter <= counter + 1;


and ucf is:

NET "clk" LOC = P56; # 50MHz

# Output

NET "tone_1khz" LOC = P57;
NET "tone_100hz" LOC = P66;
NET "tone_12khz" LOC = P74;

runs fine, but not fast enough

So my questions are:
1) even though the coregen generate seems to work, i don't seem to get the ngc file, I only get the .v and the ucf files.

2) when running core gen I have a input clock CLK_IN1 and an output clock CLK_OUT1, now I am assuming that I change all reference of clk in my code to CLK_IN1 OR CLK_OUT1, (not sure which) and recompile?

so do I replace all my clk in my original code with CLK_IN1 OR CLK_IN2.
and why would coregen not generate the ngc file?

Jeff :)

Re: Clocks and CoreGen 50Mhz > 150Mhz

Posted: January 5th, 2017, 1:28 pm
by embmicro
Hey Jeff,

I'm pretty sure CoreGen doesn't generate NGC files for the clocking wizard. It just instantiates the primitives in the .v file directly. You also don't really need the .ucf file is you have the clock constrained already (see the ucf file in the Mojo Base Project)

Simply generate the core, connect the external clk input to CLK_IN1 and use CLK_OUT1 as your system clock. You can't connect the clk input to anything else or your project will fail to build.


Re: Clocks and CoreGen 50Mhz > 150Mhz

Posted: March 17th, 2017, 8:19 am
by jkane6666

this is resolved, I generated a 300Mhz clock to get to 4 ns, the part that was missing was after the generation of the core, to attach it to the file with this

coregen_clk4 coregen_clk4(