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verilog problem

Posted: January 20th, 2016, 4:31 am
by priyesh
in verilog when we fetch data from rom to other at that time why we can not reset the signal in main code?

Re: verilog problem

Posted: January 20th, 2016, 1:13 pm
by embmicro
I'm not sure what you're asking. Maybe give us an example?