Module for Clock Generation

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fusedlightning
Posts: 13
Joined: August 4th, 2013, 5:22 pm

Re: Module for Clock Generation

Post by fusedlightning » August 19th, 2013, 9:57 am

Great, thanks!

I'm gonna go through this, and try to add it as a tutorial to my site. I'll make sure to give you credit!

-Glenn

fusedlightning
Posts: 13
Joined: August 4th, 2013, 5:22 pm

Re: Module for Clock Generation

Post by fusedlightning » August 21st, 2013, 10:12 am

Here's a little more information:

http://www.xilinx.com/support/documenta ... n6_hdl.pdf

This document shows what part-specific primitives, modules, and macros can be created to use internal chip functionality. The PLL is documented here as PLL_BASE.

I also got the core generator working! You know me though - I prefer to write it myself; I think it helps understand better.

embmicro
Site Admin
Posts: 834
Joined: March 24th, 2013, 12:45 pm

Re: Module for Clock Generation

Post by embmicro » August 21st, 2013, 1:20 pm

Yea the best way to synthesize clocks is using the CoreGen tool (from ISE go to Tools->Core Gernerator...) and using the Clocking Wizard. I'm planning to add a tutorial on the CoreGen tool soon.

Make sure you never use the output of combinational logic for a clock. This is because you can't guarantee that the output will be glitch free and can cause a lot of trouble. You should always use the FPGA's primitives to drive clocks (BUFG, DSP_SP, IBUFG, etc). This document covers the clocking resources. You don't have to worry about these if you use the clocking wizard though.

fusedlightning
Posts: 13
Joined: August 4th, 2013, 5:22 pm

Re: Module for Clock Generation

Post by fusedlightning » August 29th, 2013, 5:06 pm

Thanks! I'm on "vacation", and have been delving into the primitives. I feel more at home with these - feels almost like microcontroller peripherals!

I'm gonna go ahead and remove the code from my site, and go through clock generation in a more sane manner.

My eventual goal is to design an i2c interface for the FPGA - there are a few resources out there already, but I'd enjoy working through my own solution.

Any chance there may be a tutorial of this nature in the future?

markhu
Posts: 12
Joined: August 8th, 2013, 12:53 am

Re: Module for Clock Generation

Post by markhu » August 30th, 2013, 10:51 pm

http://hamsterworks.co.nz/mediawiki/index.php/Module_15 is the tutorial I was working from.
It uses VHDL. I heard you can mix-and-match VHDL and Verilog, but I haven't tried that yet.

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