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VHDL version of Mojo-Base project available

Posted: May 12th, 2013, 11:55 pm
by Xark

I was happy to receive my Mojo board last week and this weekend I had a bit of time to play with it, so to start I have converted the base project from Verilog to VHDL.

Nothing against Verilog, but I have been working mostly in VHDL with FPGAs (it being so different to C continually reminds me I am coding for hardware). It was also a good excuse for me to go over the Mojo AVR interface and UART code to better understand it. I thought I would provide the files in case any other Mojo developers might be interested (or have any comments on the conversion - I had to read up on Verilog just to do this).

This is pretty much a literal translation of the Verilog to VHDL and I tried to keep same signal names, structure etc. when possible (but I did attempt to add some comments - take them with a grain of salt). I also incorporated russm's suggestion about avoiding the tri-state logic warning (by adding a miso_en signal).

To help prove it is working correctly, I added a very simple process in the top level that will echo back any characters received from the USB UART as well as set the 8 Mojo LEDs to the high 8-bits of analog sample A0. Hook a potentiometer up to A0 to see the LEDs change (or even touch a wire in A0 to make them change) and connect your favorite terminal program to the Mojo COM port to see it echo what you type (I used TeraTerm).

I was able to "echo" a ~125KB text document through the test with no corruption or dropped characters (so the UART seems fairly robust).

The files should be available here: ... p/download

Please let me know if you think I have mistranslated something (or any other issue). I am no FPGA expert, but still learning as a hobby. There is an ISE 14.5 project file in the "ise_files" directory (where the resulting ".bin" file should be placed). Tested using Xilinx Webpack ISE 14.5 64-bit using Win7 and a Mojo V2 board.


Re: VHDL version of Mojo-Base project available

Posted: May 14th, 2013, 12:48 am
by leictreonaic
Great work Xark! I was trying to figure out the USB. I'm new to verilog and VHDL programming. Trying to find time to play with the thing without falling asleep on the keyboard.
I see now from your VHDL that I have to instantiate the avr interface under the mojo top file and use wires to hook up the avr ports.
Love the comments! Very easy to understand your VHDL coding.
I used your code and got the echo working with a visual basic serial port project.
I couldn't get a pot to adjust the leds. Though just touching the wire on A0 did the trick.

Now I am trying to code visual basic and the FPGA to turn on each led or select 8 bit binary number to display on leds.
Thanks for the help and intro example for VHDL.

Re: VHDL version of Mojo-Base project available

Posted: May 14th, 2013, 1:38 am
by Xark
Thanks, I'm glad you found it useful. :-)

As far as the pot, I used the center terminal of a 10K pot to A0 connector, and the other pins to AREF and GND. Just like this (except Mojo A0).

However, your "wire on a finger test" shows the FPGA is likely working fine anyways.

I was able to go from 0 LEDs to 8 LEDs quite smoothly in binary (although sometimes with a tiny bit of flicker on the low bit - so I guess the other two bits not shown may be a bit noisy - or my pot). I think the default setup may be optimized more for a fast sampling rate (and I haven't tried altering the AVR sampling parameters).

Sounds like you have a good idea to extend the project and experiment with the FPGA and communicating with the PC.

I think I would like to experiment with a "toy" CPU to make it easier for the Mojo to (e.g.) print a string on the USB UART and maybe interpret some commands sent from PC (or other input). This site had some great examples ... m#Section5

FPGAs are a bit of a "head-stretcher" coming from software programming, but I find they are fun to work with (even if not so good for getting a full nights sleep). :)

Re: VHDL version of Mojo-Base project available

Posted: May 15th, 2013, 9:03 pm
by leictreonaic
Yeah I was missing the AREF connection. Works perfect. I tested a few pots I had. 10k - 26 turn trimmer, 5k - 1 turn and 1Meg - 1 turn. Goes fast on the single turn.

Re: VHDL version of Mojo-Base project available

Posted: May 29th, 2013, 9:23 pm
by Pacemk
Thanks a lot for this ! As European, I didn't know Verilog, so a VHDL version was a useful idea !

Re: VHDL version of Mojo-Base project available

Posted: June 2nd, 2013, 6:23 am
by solidstatesoul
Massive props to Xark! I had spent ages trying to get the ADC working in Verilog with a bank of servos. Managed to get the servos going but the ADC was proving a headache (mainly due to my sketchy Verilog knowledge...) Loaded your VHDL and it just worked exactly as I'd wired it! Now trying to link in the servo part in VHDL instead, as I'm much more comfortable with this. Thanks again, really appreciated!

Re: VHDL version of Mojo-Base project available

Posted: April 29th, 2014, 9:41 am
by AerobeeHi
Hi Xark,

I'm just starting out with FPGAs and your VHDL translation has been extremely helpful for getting the hang of things.
I have a question though, why did you chose to use RTL instead of Behavioral for the architecture? I've been trying to do get myself up to speed on the differences between the two, but it's still a bit foggy. I'm hoping an example that is already somewhat familiar with might help.


Re: VHDL version of Mojo-Base project available

Posted: April 29th, 2014, 11:32 pm
by Xark

If you are referring to around line 29 "architecture RTL of mojo_top is" my understanding is that in VHDL the identifier there is "meaningless" (it can be anything, just an identifying name). Often you see "Behavioral" or "FPGA", I just semi-randomly chose to use "RTL" (which I have also seen used). This page seems to also indicate that it is just a name:

I'm glad my VHDL conversion is proving helpful to you.

Re: VHDL version of Mojo-Base project available

Posted: May 8th, 2014, 7:18 pm
by AerobeeHi
Hi Xark,

Thanks for the reply. I found another 'guide' that had some specifics about the difference between RTL and Behavioral architecture (the first page or so). I think it's just a question of what you're trying to do sequentially vs. concurrently.

I have another question though, about using multiple inputs from the ADC with your code.
In the verilog tutorial there's a capture_input module that's instantiated for each channel of the ADC you want to use. From comparing the two it seems like the same things occurs in your avr_comb process, but I'm not sure how to be able to sample multiple channels in there. I understand that the first 4 bits of the sample indicate the channel and then I get lost in all the different samples.

Sorry if this is kind of a silly question. I'm working on making my own 'capture' entity, but feeling like a real newbie.


Re: VHDL version of Mojo-Base project available

Posted: May 16th, 2014, 10:35 am
by bpenmar
Thanks Xark, your VHDL version of Mojo-Base project has been very useful to me !!

AerobeeHi, to sample multiple channels with Xark code:

if new_sample = '1' then -- if there is a new sample available then
case sample_channel is
when "0001" => Potentiometer0 <= sample; --Read the sample and set
channel <= "0111"; --the next channel to sample
when "0111" => Potentiometer1 <= sample;
channel <= "1000";
when "1000" => Potentiometer2 <= sample;
channel <= "0110";
when "0110" => Potentiometer3 <= sample;
channel <= "0001";
when others => channel <= "0111";
end case;
end if;