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output comes after 1.2 sec delay after Power ON

Posted: April 21st, 2017, 3:24 pm
by jameelaziz
hi ,
I am using XC6SLX9-2TQG144I Spartan 6 device using Mojo V3 kit

The problem i am facing problem regarding delay in output signals that
are PWM_out and Clock _out . The output is dependent upon input Clock
that is 2.097152 MHz.

The simulation doesnot show any delay but the actual hardware has timing
issue. I dont know why ? Kindly review my code by seeing its output on mojo kit.


Code: Select all

module mojo_top(      output reg  clk_out=0,
       output  reg PWM_pulse=0,
		 input clk_in,
       input reset,
       input [9:0] adc_value       
    );

		
		reg [6:0] counter_40k_clk  = 7'b0;
		reg [9:0] counter_PWM_256  = 10'b0;
		//reg [9:0] adc_value_latch  = 10'b0;
		
		
	
		always@ (posedge clk_in)
			begin
			
			if(!reset)
					begin
						counter_40k_clk <= 7'b0; //counter for generating 40khz
						counter_PWM_256 <= 10'b0;
						clk_out <= 1'b0;
					end
			
			else
			begin
					
					if ((counter_PWM_256) < adc_value)
							begin	
								
									PWM_pulse <= 1'b1;
							
							end
						else if ((counter_PWM_256) > adc_value)
							begin	
								
										
										PWM_pulse <= 1'b0;
									
							end
						else if ((counter_PWM_256) == adc_value)
							begin	
								
								if(counter_PWM_256 == 0)
										
										PWM_pulse <= 1'b0;
								else 
										PWM_pulse <= 1'b1;
									
							end	
						else
								counter_PWM_256 <=10'b0; //-- reset counter...
						
						
						counter_PWM_256 <= counter_PWM_256 +1;
						
					
				
						counter_40k_clk <= counter_40k_clk + 1;

			
						if( counter_40k_clk < 32)
							begin
								clk_out <=1'b1;
							end
						else if( counter_40k_clk < 64)
							begin
								clk_out <=1'b0;
								if( counter_40k_clk == 63)
									counter_40k_clk <= 7'b0;
							end
					
				end
		end

	

endmodule

The UCF file is as under

Code: Select all

# PlanAhead Generated physical constraints 

NET "PWM_pulse" LOC = P140 | IOSTANDARD = LVCMOS33;
NET "adc_value[0]" LOC = P139 | IOSTANDARD = LVCMOS33;
NET "adc_value[1]" LOC = P138 | IOSTANDARD = LVCMOS33;
NET "adc_value[2]" LOC = P137 | IOSTANDARD = LVCMOS33;
NET "adc_value[3]" LOC = P102 | IOSTANDARD = LVCMOS33;
NET "adc_value[4]" LOC = P101 | IOSTANDARD = LVCMOS33;
NET "adc_value[5]" LOC = P100 | IOSTANDARD = LVCMOS33;
NET "adc_value[6]" LOC = P99 | IOSTANDARD = LVCMOS33;
NET "adc_value[7]" LOC = P98 | IOSTANDARD = LVCMOS33;
NET "adc_value[8]" LOC = P97 | IOSTANDARD = LVCMOS33;
NET "adc_value[9]" LOC = P33 | IOSTANDARD = LVCMOS33;
NET "clk_in" LOC = P23 | IOSTANDARD = LVCMOS33;
NET "clk_out" LOC = P142 | IOSTANDARD = LVCMOS33;
NET "reset" LOC = P141 | IOSTANDARD = LVCMOS33;

Re: output comes after 1.2 sec delay after Power ON

Posted: April 27th, 2017, 2:47 pm
by embmicro
Are you saying nothing happens until after 1.2 seconds then the board works as expected?

If that's the case, FPGAs are RAM based meaning they need to be programmed each time power is applied. This is taken care of by the AVR on the board but can take a couple seconds. The DONE LED tells you when the FPGA has been configured.

Justin