Search found 2 matches

by maelh
September 13th, 2017, 7:30 pm
Forum: General
Topic: Lucid vs. Verilog
Replies: 3
Views: 4886

Re: Lucid vs. Verilog

Thanks. One follow up question: what is a temporary and what is a non-temporary signal?

For future reference: the part regarding always blocks in the following link helps a bit: https://en.wikibooks.org/wiki/Programma ... ing_values
by maelh
June 3rd, 2017, 5:35 am
Forum: General
Topic: Lucid vs. Verilog
Replies: 3
Views: 4886

Lucid vs. Verilog

Hi, I have been reading the reference guide for Lucid, and done some tutorials for Verilog and Lucid. Yet I could not really completely figure out what always does in each of those languages. Always is said to be about combinational logic in lucid, and the synchronous logic is probably just handled ...