Search found 4 matches

by jkane6666
March 17th, 2017, 11:09 am
Forum: Help
Topic: Shift Reg
Replies: 3
Views: 1116

Re: Shift Reg

that worked, (meaning it synthesized) but I received no output signal on p57, anyway, what I am trying to do is create a signal that is on for x number of clk pulses and then off for a different number of clock pauses. something like this _|10us|_____ 20us ______|10us|_________20us and so on (it jus...
by jkane6666
March 17th, 2017, 8:19 am
Forum: Project Ideas
Topic: Clocks and CoreGen 50Mhz > 150Mhz
Replies: 2
Views: 2408

Re: Clocks and CoreGen 50Mhz > 150Mhz

Hello,

this is resolved, I generated a 300Mhz clock to get to 4 ns, the part that was missing was after the generation of the core, to attach it to the file with this

coregen_clk4 coregen_clk4(
.CLK_IN1(clk),
.CLK_OUT1(fastclk)
);

regards

Jeff
by jkane6666
March 17th, 2017, 8:13 am
Forum: Help
Topic: Shift Reg
Replies: 3
Views: 1116

Shift Reg

Hello, I'm new to this but slightly confused, I'm trying to run this code that uses a shift register module Head_Tester #(parameter N=8) (input clk, input reset, load, input sin, input [N-1:0] d, output reg [N-1:0] q, output sout); always @(posedge clk, posedge reset) if(reset) q<=0; else if(load) q...
by jkane6666
December 8th, 2016, 8:32 am
Forum: Project Ideas
Topic: Clocks and CoreGen 50Mhz > 150Mhz
Replies: 2
Views: 2408

Clocks and CoreGen 50Mhz > 150Mhz

Hello, I am new to this so be gentle, I am trying to use coregen to change the clock frequency from 50 Mhz to 150 Mhz, I am generating a few frequencys, ie square waves, the best I can get at 50Mhz is 40ns, but I need about 10ns, so it seems that coregen is the way to go. but it does not work for me...